For example, a SiC (silicon carbide) semiconductor is excellent in dielectric breakdown resistance, thermal conductivity, etc., and therefore has been receiving attention as a semiconductor suitable to be used in, for example, an inverter of a hybrid vehicle.
FIG. 19 is a schematic sectional view of a conventional SiC semiconductor device.
A SiC semiconductor device 101 includes an N+-type 4H—SiC substrate 102 that serves as a foundation of the SiC semiconductor device 101. The SiC substrate 102 is made of SiC monocrystal, and is a substrate having an off-angle at which a surface 121, which is a Si surface defined as a principal plane on whose outermost surface Si atoms appear, is inclined in the direction of a [11-20] axis with respect to a (0001) plane. In FIG. 19, the (0001) plane in the SiC semiconductor device 101 is shown by the broken line.
An N−-type epitaxial layer 103 made of SiC doped with a lower concentration of N-type impurities than the SiC substrate 102 is stacked on the surface 121 of the SiC substrate 102. The epitaxial layer 103 is made of SiC that grows from the surface 121 of the SiC substrate 102, and has a principal plane (i.e., surface 117) parallel to the surface 121.
A base portion of the epitaxial layer 103 serves as an N−-type drain region 104 being in a constant state without being changed after the epitaxial growth. The epitaxial layer 103 has a P-type body region 105 formed on the drain region 104 contiguously with the drain region 104.
Additionally, the epitaxial layer 103 has a gate trench 106 formed by being dug downwardly from the surface 117. The gate trench 106 penetrates the body region 105 in the layer thickness direction, and its deepest portion (i.e., bottom surface 116) reaches the drain region 104. The gate trench 106 is formed in a tapered manner such that the distance between a side surface 118A and a side surface 118B that face each other becomes narrower in proportion to progress in the depth direction and such that the side surfaces 118A and 118B are inclined at taper angle θ6 with respect to a virtual surface S6 perpendicular to the surface 117 of the epitaxial layer 103.
A gate insulating film 107 made of SiO2 is formed in the gate trench 106 so as to cover the whole of the inner surface of the gate trench 106.
The inside of the gate insulating film 107 is filled with polysilicon material (N-type Poly-Si) doped with N-type impurities, and, as a result, a gate electrode 108 is embedded in the gate trench 106.
An N+-type source region 109 is formed at a surface portion of the epitaxial layer 103 on both sides in a direction (rightward-leftward direction in FIG. 19) perpendicular to the gate width with respect to the gate trench 106. The epitaxial layer 103 additionally has a P+-type body contact region 110 that penetrates a center portion of the source region 109 in the direction perpendicular to the gate width from the surface 117 and that is connected to the body region 105.
An interlayer insulating film 111 made of SiO2 is stacked on the epitaxial layer 103. Via a contact hole (not shown) formed in the interlayer insulating film 111, a source wiring 112 is connected to the source region 109, and a gate wiring 113 is connected to the gate electrode 108.
A drain wiring 115 is connected to a back surface 118 opposite to the surface 121 of the SiC substrate 102.
When a voltage exceeding a threshold value is applied to the gate electrode 108 in a state in which the source wiring 112 is grounded and in which a positive voltage is applied to the drain wiring 115, a channel is formed near an interface with the gate insulating film 107 in the body region 105, and an electric current flows between the source wiring 112 and the drain wiring 115.